1. Field of the Invention
The present invention relates to a semiconductor design support apparatus and more specifically to an apparatus and a method for supporting a layout verification process in the design of semiconductor devices.
2. Description of the Related Art
With the proceedings of the development in semiconductor technology, semiconductor integrated circuits have been increasingly loaded in various products provided in the market. The designing of a semiconductor integrated circuit can be divided into several subsequent processes: typically, a system design process, a logic design process, and a layout design process are included.
In the system design process, functions and performance of the semiconductor integrated circuit are determined based on development plans. Then, in the logic design process, a logic circuit is created which realizes the determined functions and performance. Further, in the layout design process, operation of forming the created logic circuit as a mask pattern of the semiconductor integrated circuit is performed. Typically, the semiconductor integrated circuit is configured as a combination of circuits (macrocells) collected in some unit. In the layout design process, the mask pattern of the semiconductor integrated circuit is formed by arranging the macrocells and wiring signal lines between the arranged macrocells.
To confirm in advance that the semiconductor integrated circuit can be manufactured properly by the designed mask pattern and also that the manufactured semiconductor integrated circuit properly operates, a layout verification is performed. As an example, see Japanese Laid Open Patent Application JP-P 2003-36285A which is referred to as the document D1 in the following description. This document discloses a technology related to an apparatus and a method for verifying a mask layout pattern.
FIG. 1 is a block diagram showing the configuration of the mask layout pattern verification device described in the document 1. Referring to FIG. 1, the layout verification device 110 has: an input unit 101 through which a layout pattern data file and a verification command file are inputted; a layout pattern data file storage unit 102 which stores the layout pattern data file; a verification command file storage unit 103 which stores the verification command file; an interconnection and device recognition unit 104 which, in accordance with data stored in the verification command file, recognizes interconnection and a device pattern included in the layout pattern data file; a rectangle direction and center data extraction unit 105 which extracts the direction and center coordinates data from the figure of a fuse recognized by the interconnection and device recognition unit 104; and a fuse center and direction data storage unit 106 which stores the extracted direction and center coordinates of the fuse rectangle data.
The layout verification device 110 further has: a fuse center coordinates and direction calculation formula definition file storage unit 107 which stores a fuse center coordinate and direction calculation formula definition file (hereinafter referred to as TPL definition formula file) in which the formulas for calculating the fuse coordinates are defined; a virtual fuse calculation unit 108 which calculates virtual fuse center coordinate and direction data of a verification target in accordance with the calculation formulas, constants, variables, and the like defined in the TPL file; a virtual fuse center coordinate and direction data storage unit 109 which stores calculated virtual fuse center coordinate and direction data; a fuse center coordinate and direction comparison unit 111 which compares, for a fuse as a verification target, fuse center coordinate and direction data with the virtual fuse center coordinate and direction data to determine whether or not they coincide with each other; and an output unit 112 which, based on a result of comparison performed by the fuse center coordinate and direction comparison unit 111, outputs fuse center coordinate and direction in coincided or not coincided.
FIG. 2 is an explanatory diagram showing a detailed example in which center coordinates and a long side direction are extracted from rectangle data in a conventional mask layout pattern verification device. Referring to FIG. 2, the conventional mask layout pattern verification device gets coordinates P1 (1, 1), P2 (3, 1), P3 (1, 5), and P4 (3, 5) of four vertexes of rectangle data 113 (P1 to P4), and based on these coordinates, acquires center coordinates (2, 3) and direction information, i.e., long side direction (in this example, Y-axis direction), of the rectangle data.
As described above, the conventional mask layout pattern verification device extracts center coordinates and direction information for each pattern included in a layout pattern data file, compares these extracted center coordinates and direction information with virtual fuse center coordinate and direction data serving as references, and determines the directional property of each layout pattern.
In other words, the document D1 discloses a technology by which, in a mask layout pattern verification method of a semiconductor integrated circuit, the number of vertexes and the long side of verification target data are examined to thereby select predetermined rectangle data, then coordinates of four vertexes of the selected rectangle data are extracted, and a long side direction and center coordinates of the rectangle data are calculated. Further disclosed is a technology of comparing the calculated long side direction with a direction of the reference data previously specified based on a predetermined definition formula and then determining whether or not there is coincidence in the directional property of the rectangle data.